The present invention relates in general to integrated circuits, and in particular to various circuit techniques for implementing continuous-time filters with improved performance.
The advent of cellular communication has introduced new design challenges. In, for example, code division multiple access (CDMA) cellular telephone applications, the low-pass filter that is required for filtering the base-band signal has a relatively wide bandwidth (e.g., 630 kHz). Conventional switched-capacitor (SC) techniques that are commonly used for an integrated circuit implementation of filters cannot be readily employed at such high frequencies. More specifically, the lower ratio between the sampling rate of the analog-to-digital converter (ADC) that normally receives the filter output, and the pass-band frequency of the filter, places severe design constraints on the smoothing filter that is necessary to remove the clock component from the output of the SC filter. Therefore, continuous-time circuit techniques need to be utilized to implement the filter instead of the switched-capacitor approach.
One type of continuous-time filter uses a combination of resistor R, metal-oxide-semiconductor field effect transistor (MOSFET) and capacitor C (thus the name RMC filter), along with an operational amplifier (opamp) to implement voltage-controlled integrators. An example of such an RMC filter is given in the article "Design of a low-distortion 22-kHz fifth-order Bessel filter, IEEE JSSC vol. SC-28, Dec. 1993 pp1254-1264" by U. K. Moon and B. S. Song.
Referring to FIG. 1, there is shown a conventional RMC integrator. Polysilicon resistors 108 connect to a source/drain terminal of current steering n-channel MOSFETs 110 and 112. The other source/drain terminal of MOSFETs 110 and 112 connect to the differential input terminals of opamp 116, respectively, along with integrating capacitors 114. In FIG. 1, V.sub.CP and V.sub.CM constitute the differential control voltages while V.sub.MID is mid-supply reference signal (GND). The unity-gain frequency of the RMC integrator of FIG. 1 can be adjusted by varying the differential voltage (V.sub.CP -V.sub.CM).
When such RMC integrators are used for synthesizing a signal flow-diagram of, for example, a ladder LC filter, MOSFETs 110 and 112 lie inside the local feedback loops. As a result, their non-linearity is attenuated by the loop-gain of the feedback loop. In this case, the non-linearity attenuation is mainly at low frequencies where due to the higher gain of the opamps the loop-gains are also high. For CDMA applications, however, where the filter's pass-band edge is approximately 30 times higher than that for audio applications, lower opamp gain at frequencies close to the filter pass-band may introduce unacceptably high harmonics. Higher frequency applications therefore require opamps with very wide bandwidth. Opamps with very wide bandwidth implemented in CMOS technology, however, often dissipate larger amounts of current that increase the overall power consumption and lower the DC gain for the opamp.
A second limiting factor of the RMC integrator is bandwidth limitation due to distributed parasitics of polysilicon resistors. It is generally recognized that in order to minimize the harmonic distortion in the RMC integrator, polysilicon resistors are preferred over diffused (e.g., p.sup.+) type resistors that have higher voltage coefficient. Polysilicon resistors, however, exhibit smaller sheet resistance. The smaller sheet resistance results in larger area for the polysilicon resistor and therefore larger parasitic capacitors. Such parasitic capacitors can significantly limit the overall filter bandwidth.
Another consideration in designing higher frequency continuous-time filters is variations in filter frequency response caused by variations in fabrication process, temperature and power supply. To compensate for these variations, tuner circuits have been developed that are used along with the filter to tune its frequency response. FIG. 2 shows a conventional tuner circuit. The tuner circuit includes a sine-wave voltage-controlled oscillator (VCO) 100 whose outputs connect to inputs of a comparator 102. A phase detector 104 compares the phases between an external reference square-wave CLKA and the square-wave equivalent of the output of VCO 100, CLKB. Phase detector 104 generates at its output digital UP and DN pulses for a current output charge pump 106. Charge pump 106 provides the control voltage V.sub.C to VCO 100, through its R and C loop filter components.
VCO 100 is commonly implemented using integrators similar to those used in the main filter. Conventionally, the transconductance-capacitor (g.sub.m -C) approach has been used to implement the integrators. The g.sub.m -C approach has been adopted in high-frequency applications mainly because the transconductance elements are used open-loop. Because the transconductance elements are used open-loop, however, their harmonic distortion is high. Further more, since a large input voltage is applied to the inputs of these transconductance elements their implementation for 3 volt applications adds more complexity to the design of the integrator.
There is therefore a need for circuit techniques that address the above limitations and can implement continuous-time filters with improved performance.